1. Field of the Invention
The present invention relates to a method of fabricating an electronic device using nanowires. More particularly, the present invention relates to a method of fabricating an electronic device using nanowires, capable of reducing the number of E-beam processing steps and enhancing product yields by using virtual computer-simulated electrode patterns.
The present invention has been produced from the work supported by the IT R&D program of MIC (Ministry of Information and Communication)/IITA (Institute for Information Technology Advancement) [2006-S-006-01, Components/Module technology for Ubiquitous Terminals] in Korea.
2. Discussion of Related Art
Since the development of the transistor in 1948 as an amplifying component using conductive activation in semiconductor crystalline structures, transistors have been widely being used in a variety of electronic applications such as memories or sensors. In recent years, semiconductor technologies have been geared more toward higher integration density with scale-down and lower product costs as the most important factors. Nanotechnology is now used in the semiconductor industry for the scaling-down of semiconductor devices. Low-dimensional nano-materials have different bulk and electrical, optical, chemical, and thermal characteristics due to a high ratio of surface area to volume and an effect of quantum confinement.
After confirmation by Iijima in 1991 that carbonic nanotubes (CNT) are available for use in electronic devices, numerous studies on nanowires have been proceeding vigorously. However, nanowires are regarded as insufficient in electrical uniformity and in product yield relevant to process stability and reproducibility of electronic devices using nanowires, which makes nanowire electronic devices disadvantageous to electronic device applications and mass-production. Nowadays, fabrication processes of electronic devices using nanowires generally employ patterning techniques using photolithography, electron beam (E-beam), ionic beam, X-ray, and an atomic force microscope (AFM). Research into applications of nanowires for electronic devices or integrated circuits with the above patterning techniques is actively progressing. Among said research, photolithography is most commonly used for patterning the nanowires.
Photolithography, which is a general technique for fabricating an electronic device using nanowires, includes depositing nanowires on a substrate, and forming metallic electrodes thereon through a photographic process. However, as photolithography requires E-beam or ionic beam to be used plural times, it increases the number of processing steps and degrades product yield significantly.